Location :  North America / India

• Experience in Analog Mixed-signal DDR/HBM IP layout and verification.
• Experience of high-speed digital layout and solid understanding of high speed signal
• Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies.
• Solid understanding of CMOS and FinFET layouts and process technology in 28nm and smaller.
• Good understanding of ESD and latchup layout design considerations.
• Familiarity with ASIC physical design flow: LEF generation, Place Route understanding of top level verification flow, DRC/LVS, LPE.
• Good experience in any scripting Language.
• Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc.
• Ability to foster accountability and ownership through hands-on technical leadership.
• Excellent written and verbal communication skills in interactions with customers, and internal development teams.

Responsibilities:

• High Speed DDR/HBM Layout design
• Provide subject matter expertise technical leadership in High Speed design such as DDR/HBM.
• Perform scheduling duties, Remote site interaction etc.
• Work with DDR PHY team, package engineers and system engineers to meet design specs.
• Work with cross site teams to support critical layout and floorplanning requirements

Experience:  6 to 12 years